1. Field of the Invention
The invention relates to a field effect transistor and to a method for producing a field effect transistor.
2. Description of the Related Art
In a modern so called system-on-chip circuit arrangement, it is often a challenge to integrate high-voltage interfaces on the chip. In order to satisfy the requirements of a cost effective modern system-on-chip circuit arrangement with regard to the ever increasing complexity of the logic functions to be realized and processing speed of the circuit arrangement, the integrated circuit arrangement is usually processed and produced using advanced CMOS (Complementary Metal Oxide Semiconductor) technology. In the context of advanced CMOS technology, all the process steps are usually optimized with regard to minimizing the feature sizes. In the case of the CMOS field effect transistors fabricated by means of advanced CMOS technology, this optimization usually has the effect that the CMOS field effect transistors have a low breakdown voltage on account of the underlying physical laws.
It is desirable to provide integrated circuit arrangements which can process voltages present in a range of between 10 V and 20 V. Customary standard CMOS field effect transistors have a breakdown voltage of approximately 3 V to 5 V. It is also desirable to avoid additionally required process steps in the context of the production of a suitable CMOS field effect transistor, in order not to increase the costs for the integrated circuit arrangement. It will be appreciated, however, that this arrangement has several disadvantages. The primary disadvantage is that it introduces complexity into the electrical system because of the external circuit components. This complexity is significantly increased in cases where a third power supply needs to be sequenced. Also, the cost of the system is increased as a direct result of the complexity as additional components must be added and space is required to accommodate them.
Various types of so called drain-extended field effect transistors are known which serve for integrating high-voltage driver capability into an advanced CMOS process. What is common to all these different types of known drain-extended field effect transistors is the reduction of the voltage drop across the gate oxide by implementing a space charge zone on the drain side.
FIGS. 1A, 1B and 1C show three different examples of such conventional field effect transistors. FIG. 1A shows a conventional NMOS field effect transistor 100, which has an n highly doped (n+ doped) source region 101 and an adjoining n lightly doped (n doped) drain region 102 and an n lightly doped (n− doped) first well region 103, in which an n highly doped (n+ doped) drain region 104 is introduced. Between the lightly doped drain region 102 and the first well region 103, a channel region 106 is provided in the substrate 105 made of silicon. The substrate 105 is p doped. A silicon dioxide layer 108 is applied as a gate insulation layer on the surface 107 of the substrate, and a gate region 109 made of polysilicon is applied on said layer.
FIG. 1B shows another conventional NMOS field effect transistor 120. There is introduced into a p doped substrate made of silicon 121 an n highly doped (n+ doped) source region 122 and adjoining the latter an n doped lightly doped drain region 123. An n highly doped (n+ doped) drain region 124 is furthermore provided. An n very lightly doped (n− doped) region 125 is provided adjoining the drain region 124 in the direction of the source region 122. The very lightly doped n− region 125 has an increased electrical resistance compared with the n highly doped drain region 124. A channel region 126 is provided between the lightly doped drain region 123 and the very lightly doped region 125. In the channel region, the electrically conductive channel can form if appropriate upon corresponding application of electrical potentials to the source region 122, the drain region 124 and the gate region 129. Above the channel region 126, a silicon dioxide layer 128 is applied as a gate insulation layer on the surface 127 of the substrate 121 and a gate region 129 made of polysilicon is applied on said layer.
FIG. 1C shows another conventional field effect transistor 140. The field effect transistor 140 has a p doped substrate 141, in which there is introduced an n highly doped (n+ doped) source region 142 and adjoining the latter an n doped lightly doped drain region 143. An n lightly doped (n− doped) first well region 144 is furthermore provided, in which an n highly doped (n+ doped) drain region 145 is introduced. Furthermore, in the first well region 144, an insulator structure is introduced into the first well region 144 as a trench 146 filled with electrically insulating material and adjoining the drain region 145. A channel region 147 is provided between the first well region 144 and the lightly doped drain region 143, on the surface 148 of the substrate 141 a silicon dioxide layer 149 being formed as a gate insulation layer above both the channel region 147 and a part of the first well region 144. A gate region 150 made of polysilicon is formed on the gate insulation layer 149.
FIG. 2 shows a drain-extended NMOS field effect transistor 200, the gate region overlapping a Shallow Trench Isolation (STI) region. The field effect transistor 200 has an n highly doped (n+ doped) source region 202 introduced into a p doped substrate 201, an n doped lightly doped drain region (LDD region) 203 adjoining said source region. Furthermore, an n lightly doped (n− doped) first well region 204 is provided, in which a drain region 205, n highly doped (n+ doped), is introduced. A shallow trench insulator structure 206 is formed in the first well region 204, in accordance with this embodiment described there formed as a trench filled with an electrical insulation material. Between the first well region 204 and the lightly doped drain region 203, a channel region 207 is provided in the substrate 201, in which channel region an electrically conductive channel can form given corresponding electrical driving. Above the channel region, the channel-side part of the first well region 204 and partly or completely above the shallow trench insulator structure 206, a gate insulation layer 208 made of silicon dioxide is formed and a gate region 209 made of polysilicon is formed thereon. Sidewall spacers 210, 211 are formed on the sidewalls of the gate insulation layer 208 and the gate region 209.
The field effect transistors illustrated in FIGS. 1A to 1C and FIG. 2 are based, in the context of their use, on the presumption that the gate region is always operated in a low voltage range and the high voltage (in the range of 5 V to 20 V) occurs exclusively at the drain region of the respective field effect transistor. In the case of the field effect transistors 100, 120 shown in FIG. 1A and FIG. 1B, self-aligned production of an NMOS field effect transistor is made possible by use of the lightly doped drain region 102, 123, the production of such a high-voltage field effect transistor being able to be controlled very well. However, on account of the relatively high doping concentration with doping atoms in the respective n doped lightly doped drain region 102, 123, the respective field effect transistor can only be used up to an electrical voltage present at the drain region 104, 124 with a magnitude of approximately 5 V.
For even higher voltage requirements the NMOS field effect transistor 140 illustrated in FIG. 1C is provided, in the case of which drain voltages in a range of 10 V and beyond can still be processed. This is made possible by use of the insulator structure 149. However, on account of the required mask alignment of the n well mask and the gate mask instead of the self-alignment such as can be used in the production of a customary field effect transistor, a considerable and non-negligible variation of the “effective” gate length or the channel length occurs in the production of an exemplary field effect transistor 140 in FIG. 1C, which leads to severe fluctuations in the field effect transistor parameters. The breakdown voltage, in particular, is of particular importance in the context of ESD (electrostatic discharge) protection.
The first well regions are used as space charge zones in order to reduce the voltage drop between the source region and the drain region or the drain region and the gate region. Clearly, the first well region or the very lightly doped region 125 is used as a resistance element, so that a voltage divider is formed, a voltage corresponding to the corresponding resistance of the first well region or the very lightly doped region 125 being dropped in this region and no longer between source region and drain region or drain region and gate region.
Accordingly, there is a need for less complex and low cost integrated circuit arrangement having an interface which can process voltages over a broad range.